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| TECHNICAL DATA KK74HC00A Quad 2-Input NAND Gate The KK74HC00A is identical in pinout to the LS/ALS00. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION KK74HC00AN Plastic KK74HC00AD SOIC TA = -55 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs A L L H H PIN 14 =VCC PIN 7 = GND B L H L H Output Y H H H L 1 KK74HC00A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package** Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) ** Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HC00A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Symbol Parameter Test Conditions VCC V Guaranteed Limit 25 C to -55C 0.5 1.35 1.8 1.5 3.15 4.2 0.1 0.1 0.1 0.26 0.26 1.9 4.4 5.9 3.98 5.48 -0.1 0.1 1.0 85 C 0.5 1.35 1.8 1.5 3.15 4.2 0.1 0.1 0.1 0.33 0.33 1.9 4.4 5.9 3.84 5.34 -1.0 1.0 10 125 C 0.5 1.35 1.8 1.5 3.15 4.2 0.1 0.1 0.1 0.4 0.4 1.9 4.4 5.9 3.7 5.2 -1.0 1.0 40 A A A V V Unit VIL Maximum Low -Level Input Voltage Minimum High-Level Input Voltage Maximum Low-Level Output Voltage VOUT=0.1 V or VCC=0.1 V IOUT 20 VOUT=0.1 V or VCC=0.1 V IOUT 20 VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA VIN=VIH or VIL IOUT 5.2 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 6.0 VIH V VOL V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA VIN=VIH or VIL IOUT 5.2 mA IIL IIH ICC Maximum Low-Level Input Leakage Current Maximum High-Level Input Leakage Current Maximum Quiescent Supply Current (per Package) VIL=GND VIH=VCC VIL=VCC VIH=GND IOUT=0 A 3 KK74HC00A AC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions VCC V Guaranteed Limit 25 C to -55C 75 15 13 75 15 13 10 85C 125C Unit tPLH, tPHL Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance Power Dissipation Capacitance (Per Gate) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC VIL=0 V VIH=VCC tLH=tHL=6 ns CL = 50 pF VIL=0 V VIH=VCC tLH=tHL=6 ns CL = 50 pF 2.0 4.5 6.0 2.0 4.5 6.0 6.0 5.0 95 19 16 95 19 16 10 110 22 19 110 22 19 10 ns tTLH, tTHL ns CIN CPD pF pF = 25C,VCC=5.0 V Figure 1. Switching Waveforms Figure 2. Test Circuit 4 KK74HC00A N SUFFIX PLASTIC DIP (MS - 001AA) A 14 8 B 1 7 Dimension, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 10 3.81 8.26 0.36 0.56 1.78 F L D F C -T- SEATING N G D 0.25 (0.010) M T K PLANE G H H J M J K L M N NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 012AB) Dimension, mm 8 A 14 Symbol A MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0 0.1 0.19 5.8 0.25 MAX 8.75 4 1.75 0.51 1.27 H B P B C 1 G 7 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLANE H J F M J K M P R 8 0.25 0.25 6.2 0.5 NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side. 5 |
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